The present invention relates to a synchronizing circuit, and more specifically to a circuit for synchronizing the signals between clock systems which have the same period but have a varying phase difference, or of which the phase difference undergoes a change with a change in the period thereof.
In dealing with the signals between clock systems having a varying phase difference, a variety of methods have heretofore been employed to synchronize the signals. One method consists of receiving transmitted signals by latches having a plurality of stages and clocking the signals through based upon the clock system of a receiving side. According to the above method, however, even when the time periods of the clock system signals are fixed, the time until the pulse signal is output and received by a receiving side clock remains uncertain. When the transmitter signal is received barely in time for the setup time of the latch on the receiving side, the signal pulse is lost for one period. According to another method, signal paths having different delay times are provided, and an external switch or an internal control latch is set such that an optimum signal path is selected. This method, however, involves a clumsy operation, since a given path must be selected by setting a delay time, or a given delay time must be selected beforehand and another path must be selected when given path operation is not stable.
According to the above-mentioned methods, furthermore, it is not possible to exclusively determine the path when the period varies, or when the delay time in the receiving clock system changes.